Large area polycrystalline thin-film transistors (TFTs) are often used for high performance backplanes such as, for example, for organic light-emitting diode (OLED) displays, displays with integrated control electronics, next-generation medical imaging devices, and various other types of advanced array electronics. Large area polycrystalline TFTs are usually fabricated by laser recrystallization in low temperature poly-silicon (LTPS) processing. While LTPS processing may produce good performance TFTs having a mobility of approximately 100 cm2/V-s, LTPS processing leads to significant threshold voltage non-uniformity.
Among the number of problems and shortcomings associated with current LTPS processing is that the laser tool used in such processing is widely considered to be problematic in manufacturing practices. Even more concerning is that the polycrystalline structure resulting from such processing generally leads to threshold voltage non-uniformity, as noted above, and other performance variations, largely because each device has a small and widely varying number of crystalline grains.
During recent years, there have been several attempts to make large area devices comprising single crystal islands, but none have succeeded commercially. For example, some of the techniques that are currently in development have the problem of fabricating a sub-micron seed layer, which is too small for large area lithography. Indeed, there are currently no readily available manufacturing methods for making large area arrays of single crystal islands positioned at predetermined locations.
Accordingly, there remains a need for improved processing of semiconductor components and devices, particularly with regard to single crystal TFTs.